SynaptiCAD

SynaptiCAD has developed a range of tools around timing diagrams, verification and simulation. Founded in 1992, SynaptiCAD has a long time experience with affordable, high-quality timing diagram editing tools. Since that time they have expanded the product line to include: VHDL & Verilog test bench generation, timing analysis, stimulus generation, DataBook documentation, and Verilog simulation.

Timing Diagram Editor DataSheet Pro: professional data sheet editor WaveFormer Pro: timing diagram editor + waveform translator Timing Diagrammer Pro: timing diagram editor View and export waveforms to: Agilent test equipment, Tektronix test equipment Analog and digital simulators

Verification TestbencherPro: VHDL, Verilog, and TestBuilder Graphical Test Bench Generation Transaction Tracker: Transaction Analysis with PSL/Sugar

Simulation & Debug VeriLogger Extreme: high-performance Verilog 2001 simulator BugHunter Pro: graphical debugger for all HDL simulators Gigawave Viewer: VCD/SPICE waveform viewer

Translate between Vhdl and Verilog

• V2V: do-it-yourself translation tools
• Full-service VHDL & Verilog translation: we do it for you