SynaptiCAD has developed a range of tools around timing diagrams, verification and simulation. Founded in 1992, SynaptiCAD has a long time experience with affordable, high-quality timing diagram editing tools. Since that time they have expanded the product line to include: VHDL & Verilog test bench generation, timing analysis, stimulus generation, DataBook documentation, and Verilog simulation.

Timing Diagram Editor

Timing diagram editor can display signals in different ways


Simulation & Debug

Translate between Vhdl and Verilog

Home News Products Contact Us Site Map
Copyright © 2011 HDL Works