Products

HDL Works distributes the following products:

SynaptiCAD SynaptiCAD has developed a range of tools around timing diagrams, verification and simulation. Founded in 1992, SynaptiCAD has a long time experience with affordable, high-quality timing diagram editing tools. Since that time they have expanded the product line to include: VHDL & Verilog test bench generation, timing analysis, stimulus generation, DataBook documentation, and Verilog simulation.

CAST: IP-cores

CAST is one of the oldest IP companies in the EDA industry. Their portfolio covers a broad range starting from TTL simulation models to high-end multimedia cores like the JPEG 2000. With thirteen years of experience and hundreds of successful customers, they know how to deliver IP that works. The complete, high-quality cores are ready for implementation in custom or structured ASICs or in FPGAs, and their world-wide team with a 24/7 culture provides quick, effective support.

In addition to the soft HDL cores for ASICs they also deliver firm cores and hard cores for specific FPGA vendors like Xilinx and Altera.

HDL Works performs lead generation for CAST IP-Cores in Belgium, Luxembourg and The Netherlands

HDL Works: EASE

As an experienced HDL designer you will know that an FPGA or ASIC design takes more than writing HDL code only. You will have to deal with the challenges of implementing changes that have impact on multiple places in the design hierarchy, exploring different implementations, documenting the design, integrating IP and/or functions from core generators, design reviews, working with a team of designers, etc. All these time consuming tasks are necessary, but they leave you with less time to do the job you want to focus on: the actual HDL design work.

EASE is a design entry environment that enables you to create and manage HDL projects. It will help you to perform these time consuming tasks, so you can keep your mind on the design implementation.

HDL Works: HDL Companion

HDL Companion is the SWISS Army knife for every HDL Design Engineer. It will give you a complete overview of any VHDL or Verilog design in seconds. The tool is file based and allows you to drag & drop files or directories in the user interface to create a project. It fits in all design and tool flows. Features include verification, linting and HTML generation.

HDL Works: IO Checker

When using large FPGA's on a PCB making sure that the FPGA pins are connected to the right signals is a cumbersome task. On the FPGA side the pins are assigned to the HDL signals that form the toplevel of the logic implemented on the FPGA. On the PCB side the pins have to be connected to the proper net that will connect it to other components on the PCB. Because implementation of FPGA and PCB is often done in parallel, the signal names used are not always identical.

IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. It allows the tool to validate groups of matches although individual signals can still differ.