News

TestBencher Simplifies Random Transaction Generation
Blacksburg, VA, March 16, 2011
SynaptiCAD has released a new version of TestBencher Pro, a VHDL and Verilog system-level testbench generation software that dramatically simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The new version also simplfies creation of testbenches that reside in a different compiled library from the design being tested.

SynaptiCAD's BugHunter Supports 64-bit ModelSim & Incisive Simulators
Blacksburg, VA, November 16, 2010
SynaptiCAD has released an updated version of it's VHDL and Verilog testbench generation and debugging tool, BugHunter Pro, with support for 64-bit versions of Mentor Graphics ModelSim and Cadence Incisive simulators.

WaveFormer Lite Generates Mixed Signal HDL Test Benches for all FPGA design flows
Blacksburg, VA, August 2010
SynaptiCAD has just released a major upgrade to WaveFormer Lite, it's entry level tool for generating VHDL and Verilog test benches graphically from timing diagrams drawn by the user.

SoC Solutions Builds FPGA System in Record Time Using Synopsys' ReadyIP Flow and CAST IP Cores
Woodcliff Lake, NJ, June 4, 2008
Silicon Intellectual Property (IP) provider CAST, Inc. and technical partner SoC Solutions LLC recently proved the effectiveness of a new FPGA design capability from Synopsys' Synplicity Business Group by developing a complete 32-bit processor-based system in just three and a half days.

CAST Expands System IP Offerings with Embedded Internet and USB Subsystems
Woodcliff Lake, NJ, March 7, 2008
Silicon Intellectual Property (IP) provider CAST, Inc. today announced the availability of embedded subsystems that make it easier to integrate Internet connectivity or a USB controller in system-on-chip (SoC) designs.